Chung-Hsing Hsu
Me sitting in my corner After so many years I finally got out from Rutgers University with a Ph.D. degree in Computer Science at the end of June 2003. My thesis title is "Compiler-Directed Dynamic Voltage and Frequency Scaling for CPU Power and Energy Reduction". Dynamic voltage and frequency scaling is a power saving technique that lowers the CPU voltage and frequency for power and energy savings. While lowering the CPU frequency will decrease the performance, I managed to have, on average, 20% energy reduction at 2% performance slowdown on a mobile AMD Athlon 4 processor. Currently, I am working for the Los Alamos National Laboratory on a two-year postdoc. I continue conducting research on the CPU energy reduction using dynamic voltage and frequency scaling. My general research interests are in the interaction between program characteristics, optimizing compilers, and target architectures. My full CV (updated on May 29, 2003 before I left the school) is available. If you have questions about my research or are interested in the possible collaborations, please feel free to contact me at CHUNGHSU AT LANL DOT GOV.

Publications

  • Compiler-Directed Dynamic Voltage and Frequency Scaling for CPU Power and Energy Reduction
    Chung-Hsing Hsu, Ph.D. Dissertation, June 2003.

  • The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction
    C-H. Hsu and U. Kremer
    ACM SIGPLAN Conference on Programming Languages, Design, and Implementation (PLDI'03),
    San Diego, CA, June 2003.

  • Compiler-Directed Dynamic Voltage Scaling for Memory-Bound Applications
    C-H. Hsu and U. Kremer
    Rutgers University Technical Report DCS-TR498, August 2002.

  • Power and Energy Management for Scientific Applications Based on Dynamic Voltage Scheduling
    C-H. Hsu and U. Kremer
    Rutgers University Technical Report DCS-TR497, August 2002.

  • Energy-Conscious Compilation Based on Voltage Scaling
    H. Saputra, M. Kandemir, N. Vijaykrishnan, M.J. Irwin, J.S. Hu, C-H. Hsu, and U. Kremer
    Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and
    Software and Compilers for Embedded Systems (SCOPES'02), Berlin , Germany, June, 2002.

  • Single Region vs. Multiple Regions:
    A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches
    C-H. Hsu and U. Kremer
    Workshop on Power-Aware Computer Systems (PACS'02), Cambridge, MA, February 2002.

  • Compiler-Directed Dynamic Voltage Scaling Based on Program Regions
    C-H. Hsu and U. Kremer
    Rutgers University Technical Report DCS-TR461, November 2001.

  • Compiler-Directed Dynamic Frequency/Voltage Scheduling for Energy Reduction in Microprocessors
    C-H. Hsu, U. Kremer, and M. Hsiao
    International Symposium on Low Power Electronics and Design (ISLPED'01), August 2001.
    An extended version is available as Technical Report DCS-TR431 .

  • Dynamic Voltage and Frequency Scaling for Scientific Applications
    C-H. Hsu and U. Kremer
    Proceedings of the 14th International Workshop on Parallel Computing (LCPC'01), August 2001.
    Also available as Technical Report DCS-TR447, June 2001.

  • Compiler-Directed Dynamic Frequency and Voltage Scheduling
    C-H. Hsu, U. Kremer, and M. Hsiao
    Workshop on Power-Aware Computer Systems (PACS'00), Cambridge, MA, November 2000.
    An extended version is available as Technical Report DCS-TR419 .

  • A Stable and Efficient Loop Tiling Algorithm
    C.-H. Hsu and U. Kremer
    Mid-Atlantic Student Workshop on Programming Languages and Systems, Newark, DE, April 2000.
    Also available as Technical Report DCS-TR407, December 1999.

  • Tile Selection Algorithms and Their Performance Models
    C-H. Hsu and U. Kremer
    Technical Report DCS-TR401, Department of Computer Science, Rutgers University, October 1999.

  • IPERF: A Framework for Automatic Construction of Performance Prediction Models
    C-H. Hsu and U. Kremer
    Workshop on Profile and Feedback-Directed Compilation (PFDC'98), Paris, France, October 1998.

  • A Framework for Qualitative Performance Prediction
    C-H. Hsu and U. Kremer
    Technical Report DCS-TR363, Department of Computer Science, Rutgers University, July 1998.

  • A Linear-C Implementation of Dijkstra's Algorithm
    C-H. Hsu, D. Smith, and S. Levy
    Technical Report LCSR-TR-274, Department of Computer Science, Rutgers University, September 1996.

  • Linear-C: A Data Parallel Extension to C
    C-H. Hsu, D. Smith, and S. Levy
    Technical Report LCSR-TR-273, Department of Computer Science, Rutgers University, September 1996.

  • Modeling the Performance of Hypercubes: A Case Study on Sorting Problem
    C-H. Hsu and J. Ho
    International Conference on System Research, Informatics and Cybernetics, August 1991.